Static timing analysis (STA) allows quick and comprehensive timing verification of large circuits. Compared to simulation, STA is much faster and guarantees identification of the critical paths in a circuit. Simulation, on the other hand, is impractical for large circuits because simulators are typically slow and sometimes fail to find the right input vectors to excite the critical paths. Usually, STA has three main steps: (1) calculating delays of individual gates and interconnect, (2) adding up the delays of all gates to obtain the path delays for the entire circuit, and (3) verifying the circuit constraints by checking whether certain signal transitions occur before or after certain other transitions. For gate-level circuits, a pre-characterized timing model is used for each gate type. Typically the timing models, which are part of the design library, are generated only once, allowing extensive simulations to be performed in order to accurately model each gate. For transistor-level circuits, however, there are no pre-characterized gates, and delay calculation must be performed on the fly. A well-known method for analyzing circuits of this type is circuit simulation, which produces very detailed timing information, such as waveforms and delays, by solving non-linear differential equations. However, this method is very time consuming and requires a large number of input vectors to be applied to the circuit. In addition, there are problems in finding appropriate input vectors to simulate the critical paths of a circuit. Therefore, direct use of simulation is inapplicable to large, practical circuits.
To speed up STA for transistor-level circuits, various approximation methods for delay calculation based on heuristic formulas or lookup tables have been developed. These methods provide a closed form solution to a non-linear system of equations describing gate behavior and are commonly used in delay calculators. However, as features sizes become smaller, these approximation methods become increasingly inaccurate because new considerations, which were previously neglected, must be taken into account. Enhanced models that attempt to rectify this accuracy deficiency not only become cumbersome but also produce results that under certain conditions are questionable. For high accuracy and reliability, closed form expression for delay can no longer be used. Therefore, it has become necessary to go back to the method of solving non-linear equations via numerical integration, i.e., using circuit simulation.